SX-12 In Stock

The Spirent SX/12 is a highly capable Data Link Simulator designed to replicate the delay and error characteristics typically encountered in long-distance data links, including both satellite and terrestrial connections. This simulator serves as a valuable tool for testing network applications and new equipment under controlled and repeatable conditions. Featuring full-duplex, dual-channel operation, the SX/12 enables bi-directional testing with the introduction of random bit errors, burst errors, and programmable delays. These error and delay events can be precisely programmed to simulate a wide range of periodic and chronic conditions, such as equipment overloads and peak traffic times.

One notable feature of the SX/12 is its data channel clocking, which offers multiple modes of operation. In the receive clock mode, the simulator synchronizes with an external equipment's master timer, receiving the clock signal from a separate line or recovering it from the data line. In the internal clock mode, this simulator generates the master timing using a crystal oscillator or clock synthesizer. Lastly, in the external clock mode, users can provide an external clock signal to serve as the master clock, enabling the injection of wander, jitter, and clock frequency errors. The SX/12 incorporates a built-in lithium battery with a lifespan of seven years, ensuring parameter and sequence backup in the event of power loss or disconnection.

The SX/12’s front panel features two line by 40-character display panels, providing user prompts and displaying current settings. Additionally, it includes 28 keys for parameter input and operating the simulator. For remote control and programming, the simulator supports IEEE-488 or RS-232 interfaces. With the extended T1/E1 simulation option, the SX/12 offers enhanced delay and error simulation capabilities specifically tailored for testing T1 (1.544 Mbps) and E1 (G.703 2.048 Mbps) data streams. This option allows test engineers to create precise error conditions, identifying and isolating equipment weaknesses. By assigning different delays to selected timeslots, it can stress test various systems, including T1, E1, compressed video, fractional T1, and inverse multiplexers, which rely on multiple timeslots for high-speed data transmission.

The extended T1/E1 simulation option of the SX/12 encompasses both delay and error characteristics. Delay characteristics enable the assignment of ten user-definable delay rates to each timeslot within the T1/E1 data stream. This feature allows for comprehensive stress testing and evaluation of equipment performance. The error characteristics option enables the targeting of any of the six error types to specific bits within a multi-frame. By selectively introducing errors to desired bits while leaving others unaffected, this feature facilitates the simulation of precise error conditions, including framing bit errors, sync loss, CRC errors, signaling bit errors, and data link bit errors. Error types can be fixed or random logic errors, zeros, or ones.